Memory systems may employ error coding schemes for improved reliability. For server applications, aggressive error detection/correction coding (EDC) methods, such as Single Device Data Correction (SDDC) or coding known by one form under the IBM trademark Chipkill, provide error correction capability in the event of a fault with the module associated with a memory component. One example of the Chipkill process generally involves two memory modules operating in lockstep, with the databus width (such as 144 bits) of both modules being EDC coded. Should a memory component on one of the modules become associated with a detected fault, the coding enables a reconstruction of the data associated with the failed component without the entire memory system having to go offline.
While SDDC codes like Chipkill coding often work well for their intended applications, memory modules often include many memory components. Operating two modules in lockstep generally involves activating all of the memory devices on both modules for each memory transaction. Significant power is thus consumed for each transaction. It would be desirable to have the flexibility to carry out memory transactions using less than all of the available memory components while still retaining error coding capabilities to address a majority of fault scenarios.